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created by michael munroe |
Draft Date |
Editor |
Title updated 19 December 2009 |
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Guide to color code used in the table below. |
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Standards Organizations and their web sites with documents listed. |
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Clickable “bookmarks”
above for each
organization. |
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Light gray |
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Indicates an abandoned effort |
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Tan |
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Cross Organization Activities |
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Light green Only |
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Indicates an active effort or a proposed document. |
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Other colors |
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Indicates a related group of documents under active development |
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PCI Industrial Computer Manufacturers Group |
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PICMG 1.0 R2.0 |
released 10/10/1994 |
D. Somes |
PCI-ISA
Card Edge Connector for Single Board Computers. |
| PICMG
1.3 R2.0 ECR (see list) |
Current ECR topics
for R3.0 •001 PCI Local Bus 2.2 Update •002 PCI-X Extensions •003 SBC Mechanicals •004 Backplane Mechanicals •005 Interrupt bindings •006 SMBus |
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PICMG 1.1 R1.0 |
released 5/25/1995 |
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PICMG 1.2 R1.0 |
released |
PCI This document defines the mechanical
and electrical architecture of a system with either two PCI/PCI-X
busses or a single PCI/PCI-X bus. |
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PICMG 1.3 R1.0 |
10/31/2005 released |
J. Munch |
SHB Express System Host Board PCI Express |
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PICMG 2.0 R3.0 ECR PCI-X D0.6a |
released 11/16/01 |
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This ECR was incorporated in subsequent |
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PICMG 2.0 R3.0 ECN2.-3.0-00- 002 |
released 1/23/2002 |
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Compact PCI Core Specification, with self |
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PICMG 2.1 R2.0 |
released 1/17/2001 |
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CompactPCI Hot Swap |
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PICMG 2.2 R1.0 |
released 9/9/1998 |
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VME64x on CompactPCI |
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PICMG 2.5 R1.0 |
released 4/3/1998 |
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CompactPCI Computer Telephony |
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PICMG 2.6 D0.4 |
1/12/2001 abandoned |
S. Mercer B. Robitaille |
Bridging Beyond 8 Slots: Common Practices – |
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PICMG 2.7 R1.0 |
released 4/10/2001 |
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6U CompactPCI Dual System Slot Specification |
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PICMG 2.8 D0.7? |
4/23/2001 abandoned |
D. Kelly |
Pin
Registration for PXI This became the PXI Instrumentation Bus. |
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PICMG 2.9 R1.0 ECN 001 5/20/02 |
released 5/20/2002 |
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CompactPCI
System Management |
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PICMG
2.9 IPMI Codes |
7/15/2006 |
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A
list of IPMI management codes was released in xls format. |
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PICMG 2.10 R1.0 |
released 10/1/1999 |
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Keying of CompactPCI Boards and Backplanes |
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PICMG 2.11 R1.0 |
released 10/1/1999 |
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CompactPCI Power Interface |
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PICMG 2.12 R2.0 |
released 5/20/2002 |
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Hot Swap Infrastructure Interface |
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PICMG 2.13 D0.6 |
11/29/2001
abandoned |
G. Graf |
Redundant System Slot Specification – This has been inactive long enough to pronounce “dead” |
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ICMG 2.14 R1.0 |
released 9/5/2001 |
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CompactPCI Multi-computing Specification |
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PICMG 2.15 R1.0 ECN 2001 |
released 1/22/2003 |
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PCI Telecom Mezzanine/Carrier Card Specification |
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PICMG 2.16 R1.0 |
released 9/5/2001 |
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CompactPCI Packet Switching Backplane Specification |
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PICMG 2.17 R1.0 |
released 5/20/2002 |
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CompactPCI StarFabric Specification |
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PICMG 2.18 R1.0 |
released 6/18/2004 |
A. Kaiway |
Serial Rapid IO Specification – Over CompactPCI 2.0 |
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PICMG 2.20 R1.0 |
released 10/21/2002 |
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CompactPCI Serial Mesh Backplane Specification |
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PICMG 2.30 RC1.0 |
9/23/2009 |
Manfred Schmitz |
CompactPCI Plus IO. This document will cover the implementation of PCI Express signals on the J2 connector of a CompactPCI board. A special shielded 7-row 2mm connector referred to as ultra-hard metric is utilized. This is a connector available from 3M. This document completed balloting in November of 2009. The release candidate document is 40 pages long. |
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PICMG 2.31 d0.31 |
11/30/2009 |
Manfred Schmitz |
CompactPCI
HSF.PICMG 2.31 CPCI-S CompactPCI Serial defines a new 12 row AirMax
style connector to create hybrid systems that can be comprised of a
CompactPCI Plus System board and up to 7 CompactPCI® peripheral
boards as well as up to four CompactPCI®Plus peripheral boards with limited functionality. Alternatively, full mesh systems can be supported utilizing only CPCI-S boards. The current draft is 96 pages long. |
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PICMG 2.50x Base Doc. D0.83 draft 9.0 expected soon. |
3/6/2005 |
C. Hill |
CompactTCA on 2mm HM with 3 row ADF in P4
position. This document remains under development but I am not
participating and cannot determine the current draft level. |
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PICMG 2.50 Power Control V1.0 |
2/2/2005 |
P. Hawkins |
CompactTCA Hot Swap and Power Control CompactTCA Management Sub team. This subsection discusses the special requirements on Managed FRUs for activation and deactivation in a CompactTCA® system, specifically the state definitions, messaging, and state transition sequences. These requirements deal with CompactTCA® components at the Field Replaceable Unit (FRU) level. These FRUs include CompactTCA® Boards, CompactTCA® Boards containing mezzanines, CompactTCA Power Supplies, and other FRUs such as intelligent fans and non-intelligent removable fans that are represented by IPM Controllers, and so on. |
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PICMG CompactPCI Plus |
2008 |
Manfred Schmitz |
CompactPCI Plus. This is a technical working group preparing a new specification. |
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PICMG 3.0 R1.0 |
12/30/2002 released |
J. Munch |
AdvancedTCA Base Specification. This comprehensive document has 438 pages divided into 8 chapters and 3 appendices. |
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PICMG 3.0-1.0 ECR 3.0-1.0-001 |
1/12/2004 released |
J. Kennedy |
ECR to Release 1.0 of AdvancedTCA Base Specification. This ECR incorporated a number of changes including, cooling, power distribution, lever handles and face plates. |
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PICMG 3.0 R2.0 |
9/8/2004 released |
J. Munch |
AdvancedTCA Base Specification This release includes a new Advanced Differential Fabric Connector as well as ECR 1.1 472 pages |
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PICMG 3.0-2.0 ECR 3.0-2.0-001 |
4/28/2005 released |
M Overgaard |
ECR to Release 2.0 of AdvancedTCA Base Specification. This ShMC Cross-connects ECR will add dual 10/100BASE-TX links to allow two dedicated Ethernet links to both shelf managers. This would eliminate the Gigabit Ethernet possibility for the base fabric. This ECR is now being balloted. |
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PICMG
3.0 R2.0 ECN 002- R1 |
5/26/2006 |
J. Munch |
ECR to Release 2.0 of AdvancedTCA Base
Specification. This ECR will make a
number of corrections to mechanical drawings, better define
cooling requirements, shelf management and
add a redundant dual star topology. No changes are anticipated which
would make current product obsolete. Many changes have been made to
the system management section and additional mechanical reference
designs have been incorporated for such items as front panels. The
draft document closed on April 29th. The document is now 536 pages
long. |
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PICMG
3.0 R3.0 |
3/24/2008 |
J. Munch |
AdvancedTCA Base Specification . This Release
3 draft document is now 632 pages long with 8 chapters and 5
appendicies. There are new RTM pcb dimensions as well as a revised IPMI
section. Many other changes are incorporated in this document that has
added nearly 160 pages since R2.0 and 100 pages since the May 2006 ECN
002. This document is aproximately 656 pages long. |
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PICMG 3.1 R1.0 |
1/22/2003 released |
J. Peters |
Ethernet/Fiber Channel for AdvancedTCA Systems |
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PICMG
3.1r2 |
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D. Sandy |
Ethernet Protocol Layer for AdvancedTCA. This
document is covering the implementation of 10GBase-KX4,
10GBase-KR and 40GBase-KR4 on AdvancedTCA. 40GBase-KR4 is the
subject of IEEE P802.3ba. Simulations are being undertaken to establish
the electrical channel requirements for these Ethernet protocols as
defined within IEEE 802.3-2008. |
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PICMG 3.2 R1.0 |
1/22/2003 released |
C. Byers |
InfiniBand™ for AdvancedTCA Systems |
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PICMG 3.3 R1.0 |
5/21/2003 released |
S. Cristo |
StarFabric™/Advanced Switching for AdvancedTCA Systems |
PICMG 3.4 R1.0 |
5/21/2003 released |
T. Fountain |
PCIExpress™/Advanced Switching for AdvancedTCA Systems |
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PICMG 3.5 R1.0 |
10/17/2005 released |
C. Hill |
Rapid IO™/Advanced Switching for AdvancedTCA
Systems. In this new document add in cards must identify their
signaling method before they are allowed to participate. The Rapid IO
signaling architecture is available from www.rapidIO.org |
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PICMG
3.6 PRS |
6/28/2005 |
Pierre Planas |
Packet Routing Switched Architecture (PRS)
Cell switching architecture (PRS) over the
dual star and mesh topologies of PICMG 3.0. I do not
have any current information on this document. |
PICMG 3.8 D0.? |
1/2004 |
R. Davidson |
Classification of AdvancedTCA Applications |
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PICMG AdvancedTCA RTM Interface (ARTM) draft 0. |
x/2009 |
D. Slaton |
AdvancedTCA RTM Interface Solution for AMC modules. |
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PICMG
AdvancedTCA Extensions (IRTM) draft 2.4 |
9/2009 |
C. Engels |
AdvancedTCA Intelligent Rear Transition Module specification. This draft document is now 37 pages long. |
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PICMG
XTCA f Physics no draft |
9/2009 |
R. Larson |
AdvancedTCA and MicroTCA Extensions for Physics. |
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PICMG
XTCA Software |
9/2009 |
S. Simrock |
xTCA Software Architecture Protocols |
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PICMG
XTCA Timing |
9/2009 |
R. Downing |
xTCA Timing and Synchronization. An
AdvancedTiming specification TIM.0 Rev 1 draft 0.1 dated 9/15/2009 has
been proposed. |
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PICMG AdvancedMC™.0 R1.0 |
1/3/2005 released |
M. Summers |
AdvancedMC™ Advanced Mezzanine Card Base
Specification. This is a 294 page specification covering all the system
management,
mechanical structure, electrical interface requirements for this
mezzanine
module system that is hot pluggable. In July 2006, the executive
committee proceeded with the AMC trademark by limiting the claimed
applications. Release 2 incorporated new clock circuits. |
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PICMG
AdvancedMC™.0
ECN001 R.1.0 |
6/26/2006 |
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ECR001 is now a released specification.
This 60 page document incorporates some 3,362 ECRs and is based on
draft 0.9. |
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PICMG
AdvancedMC™.0 ECR002 R.1.0 |
11/15/2006 |
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ECR002 to PICMG AMC.0 CRs resolved
3,362 ECRs listed. This 342 page
document is approved . |
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PICMG
AdvancedMC™.0 R2.0 |
11/16/2006 |
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PICMG AdvancedMC .0 is incorporates
ECN001 and ECN002 and is 372 pages long. |
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PICMG AdvancedMC™.1 R1.0 |
2/22/2005 |
L. Guthrie |
AdvancedMC™ PCI Express and Advanced Switching on AMC modules |
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PICMG AdvancedMC™.1 R2 |
10/8/2008 |
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AdvancedMC™ PCI
Express and Advanced Switching on AMC modules Release 2. |
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PICMG AMC.2 R1.0 |
3/1/2007 released |
A. Dickman |
AMC
Gigabit Ethernet/10 Gigabit XAUI Ethernet A subsidiary specification to AMC.0 Gigabit Ethernet on Advanced Mezzanine Card. This AMC.0 subsidiary specification will define Gigabit and 10XGigabit Ethernet using XAUI interface and support mapping for at two channels. This document is 44 pages long. |
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PICMG AMC .3 R1.0 |
8/25/2005 |
L. Lammers |
Storage on Advanced Mezzanine Card. This AMC.0 subsidiary specification will define storage interface port usage and support mapping for Serial ATA, Serial Attached SCSI and Fiber Channel. This document is 25 pages long. |
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PICMG AMC .4 R1.0 |
7/11/2009 |
J. Montgomery |
RapidIO on Advanced Mezzanine Card. This will define lane usage optimized for a RapidIO environment. This document includes implementation guidance for specific configurations |
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PICMG AMC .Y SOW |
10/28/04 |
t.b.d. |
FibreChannel on Advanced Mezzanine Card. This AMC.0 subsidiary specification will define lane usage optimized for a Fiber Channel environment. |
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PICMG ARTM draft 0. |
x/2009 |
J. Marden |
AdvancedTCA RTM Interface Solution for AMC modules. |
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PICMG 3.300 Revision 1 |
10/10/2007 discontinued |
N. Robinson |
ATCA300 describes an 8U x 220 mm AdvancedTCA format that is compatible with the front load ETSI
300 enclosures. Adequate
clearance is provided for SFP optical module IO and a special recessed
front panel allows AMC modules to be accommodated. This document is 194
pages long and includes extensive updates to the Power Inlet
Modules, and other telecom requirements such as hold up time.
This document is currently in the executive member ballot process. |
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PICMG ASI Switching CORE Architecture
Specification Rev 1.0 |
12/2003 |
ASI SIG |
ASI Advanced Switching CORE Architecture Specification This is the complete architecturaql specification for Advanced Switching of PCI Express® Based Systems. This 366 page document was developed by the ASI SIG and turned over to PICMG in February of 2007 |
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PICMG ASI Switching Portal Rev 1.0 |
9/2004 |
ASI SIG |
ASI Advanced Switching Portal Specification A Standard Interface for Accessing the AS Fabric for PCI Express® Based Systems. This 43 page document was developed by the ASI SIG and turned over to PICMG in February of 2007 |
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PICMG ASI Protocol Interface Number 8
(ASI-PI-8) R1.0 |
2/2004 |
ASI SIG |
ASI Advanced Switching Protocol Interface Number 8. This 100 page document was developed by the ASI SIG and turned over to PICMG in February of 2007 |
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PICMG ASI Socket Data Transfer(ASI-STD)
R1.0 |
2/2004 |
ASI SIG |
ASI Advanced Switching Socket Data Transfer Specification. This 140 page document was developed by the ASI SIG and turned over to PICMG in February of 2007 |
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PICMG ASI Simple Load/Store Specification
(ASI-SLS) R1.0 |
2/2004 |
ASI SIG |
ASI Advanced Switching Simple Load/Store Specification. This 70 page document was developed by the ASI SIG and turned over to PICMG in February of 2007 |
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PICMG ASI Simple Queing Protocol (ASI-SQP)
R1.0 |
2/2004 |
ASI SIG |
ASI Advanced Switching Simple Queing Protocol. This 50 page document was developed by the ASI SIG and turned over to PICMG in February of 2007 |
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PICMG COM .0 xpress Module RC 1.0 Base |
7/10/2005 released 12/05/2005 |
B. Pebly |
Modular system based on 95 x 125 mm stamps. Allows the partition of processor, north bridge, south bridge or even NP based on PCIxpress serial IO A Computer-On-Module, or COM, is a module with all components necessary for a bootable host computer, packaged as a "super" component. A COM requires a "carrier board" to bring out I/O and to power up. COM modules are used to build single board computer solutions. |
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PICMG COM 0 R2.0 draft 0.96 |
12/9/2009 |
J. Munch |
COM 0 R2 is a revision of the COM 0
Express specification. The current revised document is 133 pages long. |
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PICMG COM-X |
10/1/2009 |
Avantech |
COM X is intended to be a small form factor legacy free highly integrated computer module supporting all current serial fabrics. The group is just forming and no draft is yet available. |
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PICMG Express 0.1 draft |
1/ 2004 |
Became 1.3 |
PCI Express on PICMG 1.0 |
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PICMG Express 0.2 draft |
1/ 2004 |
Became 1.3 |
PCI Express on PICMG 1.2 |
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PICMG EXP.0 R1.0 RC 1.0
|
5/22/2005 |
M. Wetzel |
CompactPCI Express – This 174 page
specification covers 3U and 6U
Eurocard implementation of PCI Express and PCI Express AS with system configurations defined for supporting legacy CompactPCI slots, pure Express slots and slots with both legacy and Express functionality. Both 3U and 6U applications where the lower 3U utilizes a combination of 3-row ZD, 2mm HM and 7 position UPM connectors and the upper 3U section implemented with standard P3, P4 and P5 CompactPCI connector and signal provisions. Detailed electrical requirements as well as full mechanical guidance are provided. |
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PICMG HPM.1 R1.0
|
7/7/2007 released |
B. Rosenkrantz |
Hardware Platform Management IPM Controller Firmware Upgrade Specification. AdvancedTCA intelligent FRUs may be complex enough devices to have software that will require an upgrade during the life of the board. However, even the simplest intelligent FRU has an IPM controller and this device has firmware that also may require an upgrade during the life of the product. Such upgrades may be for a number of reasons such as fixing bugs that are discovered. Another reason for an upgrade is to maintain compliance to requirements that may have changed. This 66 page document addresses the procedure and methods available to accomplish a firmware upgrade to the Intelligent Platform Module (IPM) Controller. This document is released. |
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PICMG ICCC -
Rev 0.59 |
1/9/2009 |
M. Munroe |
PICMG Interconnect Channel
Characterization
Methodology. This activity will define terminology, provide channel
diagrams and catalog various characterization methods and analytical
techniques. Data file structures for display and exchange of channel
data will be proposed. This group is not developing new methods nor is
it deciding which methods are to be used. This is to be a CORE document
that will provide content that can be used to update the electrical
requirements portion of various PICMG architectural specifications and
other similar serial architectures. This document will be
reorganized as soon as the current document has been updated with all
changes from the last ballot. The document is now 68 pages long. The
document recently lost its draft editor. |
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PICMG
MicroTCA RC 1.0 |
7/7/2006 |
M. Franko |
Micro Telecom Computing Architecture Base Specification. Granular passive host system for granular switched AMC farm. 4U x 19” x 300mm deep with 8” (200mm/side) Cube. 10-60 watt per AMC , 12V to AMC, life span 999-9999/8 years $500, cost reduced, radial IPMI-aTCA system management, 1-40 Gb/s SERDES backplane bandwidth, star, dual star, mesh, Multiple AMC support, hot swap and plug and play support Three connector designs have now been chosen to cover through hole, SMT and compression implementations. This document now has a complete list of requirements to aid in the development of compliance documents. The document is now 538 page long. This standard passed executive ballot and was announced on July 7th. It is now being prepared for publication. |
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PICMG
MicroTCA .1 R1.0 |
3/19/2009 |
M. Franko |
The Micro Telecommunications Computing Architecture Rugged Air Cooled Specification . This document covers rugged air cooled applications for MicroTCA. |
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PICMG
MicroTCA .2 |
6/19/2007 |
C. Campbell |
Hardened Convection Cooled MicroTCA. The Micro Telecommunications Computing Architecture Hardened Air Cooled MicroTCA. This document will not be worked on until the completion of MicroTCA.3 |
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PICMG MicroTCA .3 |
12/2/2009 |
M. Palis |
Hardened Conduction Cooled MicroTCA. This specification .3 covers conduction cooled clamshells and is currently planning a series of tests to confirm that the gold finger connectors will continue to perform properly within the clamshell during shock and vibration. Four new temperature classes at the most extreme levels of shock and vibration have been added to VITA 47 to support this document. An integrated draft document is not yet available. The Test Plan 1.1 has been released. |
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PICMG PSMA |
Liaison |
D. Somes G. Nanninga |
Memorandum of understanding MOU has been executed with the Power Sources Manufacturers Association. |
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PICMG
RES draft sec 1, 2, 7, 8 |
7/12/2006 |
K. Sjoblom |
The Requirements Engineering Subcommittee (RES) is
preparing lists of specific requirements for various PICMG
specifications. They are currently addressing PICMG 3.0 and have
recently released an updated list of requirements for section 2. Work
has been begun on sections 3, 4, 5, 6, 7 and 8. This is a highly
detailed effort and will allow compliance documents to be created. A 21
page master Glossary has beeen released dated August 29, 2007 it was
compiled from glossaries from the different PICMG documents including
AdvancedTCA®, Advanced Mezzanine Card™, MicroTCA™, CompactPCI®,
ompactPCI®Express and reconciled differences to compile a glossary
with over 350 definitions. |
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PICMG SAF |
liaison |
D. Somes H. Turko |
Service Availability Forum
is a
joint project for
the remote management of aTCA with both DMTF and
SMTP based management. Force,
Motorola, HP, Radisys, Intel, Sun |
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PICMG SFP.0 RC 1.0 of R1.0 |
3/25/2005 |
M. Rush |
System Fabric Plane
Format Note that a
System Fabric
may be implemented as: a LAN between
blades in a
backplane, a LAN that spans
multiple
backplanes, a private LAN
between Rack |
|
ICMG SFP.1 RC1.0 of R1.0 |
3/25/2005 |
M. Rush |
System Fabric Plane Internal TDM |
PICMG XMC Extensions |
liaison |
|
To support the VITA 42.0 XMC sockets on PICMG
form factors
and connectivity. This activity is close to completion as VITA
42.0 has been approved and released as a trial use standard. |
PICMG Requirements
Engineering (RES)
|
2/7/2006 |
K. Sjoblom |
The proposed technical subcommittee will
produce a set of organized requirements intended to help facilitate the
interoperability of equipment based upon PICMG specifications. This
activity will work in conjunction with SCOPE a special interest group
made up of TEMs including Alcatel, Ericsson,
Motorola, NEC, Nokia and Siemens http://www.scope-alliance.org/index.html
This group now has a formal Statement of Work. Recently an enumeration
scheme has been proposed. |
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PCI to PCI Bridge |
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Conventional PCI 2.2 |
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Revision 2.2 defines the PCI hardware environment including protocol, electrical, mechanical and configuration specifications as well as expansion boards. Seventeen ECRs are incorporated including six mechanical ECRs |
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Conventional PCI 2.3 |
|
|
Revision 2.3 migrates the PCI
bus from 5.0
volt signaling to 3.3 volt signaling and supports the 5V and 3.3V keyed system board connectors but only supports the 3.3V and Universal keyed add-in cards. The 5V keyed add-in card is not supported in revision 2.3. |
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Conventional PCI 3.0 |
|
|
Revision 3.0 completes the
evolutionary
migration plan for the PCI Local Bus Specification, migrating the PCI bus from the original 5.0V signaling to a 3.3V signaling bus. Revision 2.3 began that evolution by removing support for the 5V keyed add-in card, while providing support for both the 5V and 3.3V keyed system board connectors. Revision 3.0 takes the next step of removing support for the 5V keyed system board connector. Revision 3.0 continues support for the 3.3V keyed system board connector, which supports the 3.3V and Universal keyed add-in cards. |
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PCMCIA |
|
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PCI Card Bus |
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PCI-X 1.0 Electrical & Mechanical Spec. |
|
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Revision 1.0 of the PCI-X specification defines PCI-X 66 and PCI-X 133 |
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PCI-X 2.0a Electrical & Mechanical
Spec. |
2/5/2002 |
|
Revision 2a Migrates PCI-X 266 and PCI-X 533 while retaining hardware and software compatibility with previous generations of PCI and PCI-X. |
|
PCI/PCI-X Contact Finish ECN |
|
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Connector contact finish specification. |
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PCIe Base Module Spec 1.0a |
7/23/2002 |
|
PCI Express formerly 3GIO high-speed serial interconnect specification Revision 1.0a includes both the Base and Card Electromechanical 1.0a specification documents. PCI Express includes such features as, QoS, power management, native hot-plug, higher bandwidth, error reporting, recovery and correction new form factors. The PCI Express unifies general-purpose I/O and graphics I/O and provides a linearly scaled 16-lane interconnect that supports data transfer rates greater than 8 GB/s. |
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PCIe CEM Spec 1.1 |
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PCIe Mini CEM Spec 1.1 |
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PCIe Base PCI Bus Power Management Draft ECN |
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April 1, 2005 member review ends |
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PCI Express Advanced Switching |
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Scalable Serial PCI Express Switched Fabric |
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PXI
Systems
|
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|
|
PXI Specification Rev 1.0
|
8/20/1997 |
|
PXI Specification Extensions for Instrumentation |
PXI Specification Rev 2.0 |
7/28/2002 |
|
PXI Specification Extensions for Instrumentation |
PIXY Hardware Spec. Rev 2.1 |
2/4/2003 |
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PXI Hardware Specification Extensions for Instrumentation |
PXI-1 Rev 2.21 Hardware Spec. |
9/22/2004 |
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PXI Hardware Specification Extensions for Instrumentation on 3U Eurocard CompactPCI Express |
PXI-1 Rev 2.2 ECN -1 Hardware Spec. |
5/12/2005 |
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ECN-1 to PXI Hardware Specification Extensions for Instrumentation on 3U Eurocard CompactPCI Express |
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PXI-2 Software Spec R.2.1 |
2/4/2003 |
|
PXI Software Specification |
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PXI -3 VISA for PXI Spec R1.0 |
9/25/2003 |
|
VISA for PXI Specification |
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PXI -4 PXI Module Spec. R1.0 |
9/25/2003 |
M. Wetzel |
PXI Module Specification |
|
PXI-5 Express Hardware Spec. |
8/22/2005 |
M. Wetzel |
PXI Express Hardware Specification |
|
PXI-5 Express Hardware Spec. Rev 1.0 ECN 1
Draft 0.2 |
2/6/2006 |
M. Wetzel |
PXI Express Hardware Specification Release 1.0 ECN 1 This 5 page revision was required to address the lack of XP8/XJ8 pin assignments which are necessary for 6U implementations. The maximum continuous current is also adjusted for systems with the XP8/XJ8 connector. |
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PXI-6 Software Specification |
9/1/2005 |
|
PXI Express Software Specification |
| PXI
Specification Overview |
9/12/2000 |
The
PXI Modular Instrumentation Architecture. This 8 page document was
released in September of 2000 and therefor does not mention PXI
Express. |
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| PC/104
Embedded Consortium |
http://www.pc104.org |
||
| PC/104
version 2.5 |
11/2003 |
A
specification for 8 and 16 bit 80X86 based stackable modules based on a
3.6" x 3.8" card size. The stacking connector supports the 104 pin ISA
bus by use of 64 pin and 40 pin connectors. |
|
| PC/104
Plus version 2.0 |
11/2003 |
This
specification adds a 4 column x 30 row 2.0 mm grid connector to the
PC.104 board to allow the support of 32 bit PCI signals. PC 104 Plus
does not support the 64 bit PCI extensions. |
|
| EBX
version 2.0 |
3/1/2005 |
This
Embedded Board eXpandable specification enlarges the PC/104 board size
to 5.75" x 8.0". This larger size allows the base board to support
additional features such as video, Ethernet, power connectors and
taller components such as a processor heat sink as well as a full
PCMCIA card slot. |
|
| EPIC
version 2.0 |
2/27/2006 |
This
Embedded Platform for Industrial Computing specification defines a
4.528" (115 mm) x 6.496" (165 mm) board
size which is midway between the EBX board size and the PC/104 plus
board size. This size allows the integration of more functions on the
base board than PC/104 Plus while still maintaining a relatively small
footprint. |
|
| EPIC
Embedded Platform for Industrial Computing |
http://www.epic-express.org |
||
| EPIC
Express Platform draft 0.8 |
8/26/2005 |
This
is an extension to the EPIC standard for stackable PCI Express modules.
This document was developed by AMPRO, Micro/Sys, Octagon Systems, Versa
Logic and Win Systems and is 20 pages long. |
|
| NASA Langley SPACE 104 |
|||
| RSC
Mezzanine (no document currently available) |
5/7/2006 |
R.
F. Hodson |
The
Reusable Scaleable Computer module incorporates the PC/104 Plus
architecture into a 11.25 mm x 155 mm shielded conduction cooled form
factor for use in space applications. There does not seem to be any
formal specification that is available to the public however, modules
have been built in a collaboration between the University of
Queensland, Brisbane and NASA Langley Research Center. For more
information contact robert.f.hodson@nasa.gov |
VITA/ANSI Standards |
|
|
|
ANSI VITA 1 - 1994 R2002 |
5/24/1999 |
F.Hom J. Black P. Borril W. Fischer C. Mackenna M. Pauker E. Waltz L. Hevle |
VME64
– A 287 page specification. Follows IEEE 1014/D1.2 (also IEC 821Bus)
which followed the VITA VMEbus Specification Manual Revision C.1
October
1985 which was the beginning of VITA under Lyme Hevle. Kim Cloohessy
was the technical chair and Ray Alderman was the executive chair
running interference with the IEEE. Frank Hom recreated most of the
drawings. John Peters is credited with originating the concept of the
64bit solution. Other
contributors to these documents were |
|
ANSI VITA 1.1-1997(R2002) |
10/7/1998 |
W. Fischer |
VME64 Extensions – This 88 page specification incorporated the 5 row IEC 61076-4-113) backward compatible backplane connector, shielded front panels, module keying, module grounding and 2eVME signaling. |
|
VITA 1.1a-200X draft 0.0 |
3/2005 |
D. Debock |
A proposed extension of the VME64 Extensions standard by use of a proposed 7 row DIN for the purpose of introducing a high-speed serial fabric bus. Harting continues to elaborate on its connector concept. |
|
ANSI VITA 1.x D0.1 |
5/22/1995 abandoned |
W. Fischer |
VME64 Extensions Test Report on New ETL Devices, New 160 Pin Connectors & 5 VME64 Extension Backplane became VITA 1.5 and 1.1 |
|
VITA 1.xx D0.1 |
8/30/1995 abandoned |
W. Fischer |
This was a specification for a next generation VME |
|
NCI VITA 1.3-1997(R2003) |
6/9/1998 |
B. Downing |
VME64 9U x 400 mm Format |
|
VITA 1.4 draft 0.5 |
12/3/1998 abandoned |
L. Francz |
VME64 Live Insertion Live Insertion System Requirements- became ANSI-VITA 3 became a board only live insertion documents. |
|
ANSI VITA 1.5-2003 |
6/2003 |
M. Rush |
American Nat. Std. for 2eSST (VME64) |
|
ANSI VITA 1.6-2000 |
2000 |
H. Sherfinsky |
Keying for Conduction Cooled VME64x |
|
ANSI VITA 1.7-2003 |
8/2003 |
R. Patterson |
Increased Current Level for 96 Pin and 160 Pin DIN/IEC Connector Standard |
|
VME320 (not a VITA or ANSI standard) listed here because of its use with VME64x board technology. |
4/15/1996 |
D. Berding F. Hirsch |
Developed
and patented by Drew Berding in conjunction with Bustronic Corporation,
this effort was supported by VITA in a marketing campaign. VME320
utilizes an ingenious star backplane design, tapered trace construction
and special diode terminations to allow the VME architecture to
function as an incident wave, point to point system with conventional
bus drivers. These techniques described in three patents allow VME
transfers at rates up to 320 Mbytes/sec. The backplanes are built under
license from Arizona Digital, Inc. or its agent Bustronic, Inc. Later,
it was shown how this technique could achieve data transfers up to 533
Mbytes/sec. Later |
|
ANSI VITA 2.1-199x D0.5 |
8/22/1997 |
E. Barsotti abandoned |
Requirements For 2eVME & 2eSST-Compatible Drivers, Receivers and Transceivers. This work resulted in the development of the TI-Universal Bus Transceiver. Testing of initial devices was reported on 3/25/2002. Further work was tabled in May of 2002. The task group results were subsequently incorporated into relevant VME documents such as VITA 1.5. |
|
VITA VME1000 |
7/16/1998 |
A. Lenkisch abandoned |
This series of technical reports was a further extension of the earlier VITA 2.1 Task Group investigation... This work appears to have lead to the ETL device development which resulted ultimately in VITA 1.5. A Hybricon report dated 6/14/1999 is the last document related to this effort. |
|
ANSI VITA 3-1995(R2002) |
2002 |
R. McKee |
Board Level Live Insertion for VMEbus. This document represents a methodology or recommended cards in an operating VMEbus system. This document does not detail a point solution; this is left to the implementer. The primary directive practices guide for inserting or extracting VMEbus when defining this methodology was to maintain maximum compatibility with existing off-the-shelf VMEbus boards. |
|
ANSI VITA 4-1995(R2003) |
2002 |
K. Rubin |
IP Modules |
|
ANSI VITA 4.1-1996(R2003) |
2003 |
K. Rubin |
IP I/O Mapping to VME64x |
|
ANSI VITA 5.1-1999 |
8/31/1999 |
B. Blau |
RACEway Interlink - This standard defines a high speed circuit switched point to point interconnect for use between VMEbus modules via the P2 connector. |
|
VITA 5.2-200X |
5/12/2004 |
T. Lavely |
RACE++ - This standard will document the RACE++ architecture which has become a de facto replacement for RACEway Interlink in the marketplace. |
|
ANSI VITA 6-1994 (R2002) |
2002 |
L. Francz |
SCSA - This standard defines an isochronous backplane bus for telephony applications on the VMEbus P2 connector. |
|
ANSI VITA 6.1-1996 (R2003) |
2003 |
L. Francz |
SCSA Extensions - This standard provides feature extensions to the ANSI/VITA 6 standard. |
|
ANSI VITA 10-1995 (R2002) |
2002 |
R. Jan |
SKYchannel - A packet switched cross bar interconnect that runs on the VMEbus P2 connector |
|
ANSI VITA 12-1997(R2002) |
2002 |
|
M-Module – Defines a mezzanine module specification for small sized printed circuit boards. |
|
ANSI VITA 13-1995 |
7/16/1966 |
C. Whitby-Strevens |
VMEbus Pin Assignment Standard for ISO/IEC 14575 (IEEE Std. 1355-1995 (H.I.C.)) – Defines a pin assignment for the VMEbus to support the Heterogeneous Interconnect protocol standard defined in IEEE 1355. |
|
ANSI VITA 17-1998 |
2/11/1999 |
J. Jones |
Front Panel Data Port. A specification known as FPDP defines a high-speed digital data protocol over an 80 position flat ribbon connector. This data transfer interface is typically implemented over a flat ribbon cable between two boards across their front panels that would otherwise use a fiber optic link. |
|
ANSI VITA 17.1-2003 |
6/2003 |
R. Taulton
|
|
|
VITA 17.2 d0.4 |
9/12/2006 |
J. LaLone |
Serial
Front Panel Data Port (SFPDP) Channel Bonded Protocol Draft Standard.
This standardization effort has been revived to
define a 10
Gigabaud serial file transfer protocol suitable for front panel or
backplane applications. This document is now 48 pages long. |
|
VITA 18-1997 canvas ballot Set 1999 |
1997 |
B. McKee abandoned |
VME
on SEM E modules. This document appears to have been abandoned. The
last version of the document that I could find was D1.3 dated 5/14/1997. |
|
VITA 19.0-1997 |
6/13/1997 |
P. Fischer |
Summary and Introduction to the BusNet Standard |
|
ANSI VITA 19.1-1998 |
3/11/1999 |
P. Fischer |
BusNet Media Access Control (MAC) Specification |
|
ANSI VITA 19.2-1998 |
3/11/1999 |
P. Fischer |
BusNet Link Layer Control (LLC) Specification |
|
ANSI
VITA 20-2001 (R2005) |
2/20/2005 |
J. Kwok |
CCPMC
- Conduction Cooled PMC - This standard defines the mechanical
requirements for compliance with conduction cooled PMC modules. This 21
page reaffirmed document not contains a reference to thermal corrosion
due to vibration. |
|
VITA 22-199x D0.1 |
2/6/1997 |
|
ATM Cells Bus (ACB) on VME – This is a serial fabric implemented on a VME 2mmHM P0/J0. This standard is based upon TransSwitch architecture. |
|
ANSI
VITA 23-1998 (R2004) |
2/2004 |
B. Downing |
VME64 Extensions for Physics and Other Applications (VIPA). This 6U backplane standard includes lots of good 9U implementation information and supplier references. Additional power capability and additional signals are provided many of which are located on the P0 connector. It is also known as VME64xP is as well as 64x standard for physics. This 125 page ANSI VITA document was reaffirmed in 2004. |
|
ANSI VITA 25-1997 |
10/7/1998 |
J. Pangburn |
VISION (Versatile I/O Software Interface for Open-bus Networks) - A software application interface for VMEbus modules. |
|
ANSI VITA 26-1998 (R2003) |
2003 |
D. Cohen |
Myrinet - This standard defines a packet switched interconnect protocol for implementation in a VMEbus environment. This 54 page document was reaffirmed in 2003. |
|
ANSI VITA 29-2001 |
10/2001 |
K. Rubin |
PC MIP Specification – A small form mezzanine module based on the PCI bus. |
|
ANSI VITA 30–2000 |
8/2000 |
E. Parsons |
2mm Connector Practices for Euroboard Systems |
|
VITA 30–2000 d 0.1a |
7/23/2001 abandoned |
L. Francz |
A proposed revision to the 2mm Connector Practices for Euroboard Systems. Originally requested by Lou Francz, this revision was to incorporate layout guide lines for implementing the differential connector known variously as the HM-Zd, ZD or more recently the ADF (Advanced Differential Fabric) connector. When PICMG aTCA departed from a Eurocard format, this became unnecessary. |
ANSI VITA 30.1–2002 |
8/2002 |
R. Somes |
2mm
Connector Practice for Conduction Cooled Euroboards – This defines a 6U
implementation of 2mm HM in a CompactPCI layout on a daughter card
utilizing a cold plate. It defines keep out areas necessary for use
with clamping card guides. This standard just failed to achieve
an acceptable number of returned ballots during a reafirmation ballot. |
IEC VITA 30.2-2001 |
5/2001 |
L. Francz, E. Parsons |
Separable
Power Connector Equipment Practice – Defines the pin out implementation
and provides power rating curves for a wide variety of power connectors
that can be used in 6U-160 board applications such as was initially
defined in PICMG 2.0 R1.0 |
VITA 31-200X draft 0.5 |
1/9/2001 abandoned |
M. Thompson |
Serial I/O on 2 mm Connectors (P0) and cables as used in VITA 31.1 This document ended with draft 0.5. VITA 31.1 included enough mechanical data to be self sufficient and the effort begun on VITA 41 made any further P0 efforts unlikely. |
ANSI VITA 31.1-2003 |
6/2003 |
M. McPherson |
Gigabit Ethernet on VME64x Backplanes – This defines the use of a PICMG 2.16 switch fabric in conjunction with a VME64x environment where the node cards are 6U VME cards with 4 Tx pairs and 4 Rx pairs located in the upper rows 2-5 of the VME P0 connector. Rows 1 and 6 are ground rows. A standards PICMG 2.16 switch card would be implemented within one or more slots of the VME64x backplane. |
ANSI VITA 31.2 no draft |
11/20/2003 |
|
Star Fabric on VME64x P0 Backplanes - This activity was introduced at the November VSO meeting. |
ANSI VITA 32-2003 |
7/ 2003 |
G. Novak |
Processor PMC- This standard is consistent with IEEE 1386 (CMC) and IEEE 1386.1(PMC) with the exception that some previously undefined pins are assigned to processor functions and a tall format mezzanine height is defined to allow the space for larger components such as heat sinks. |
VITA 34.0 draft 0.11 |
6/5/2001 abandoned |
B. Downing |
A Scalable Modular Electromechanical Architecture. This was mainly a concept effort for power, cooling and form factor. VITA 48 appears to be a practical implementation of the most practical features. |
ANSI VITA 35-2000 |
4/2000 |
J. Kwok |
PMC-P4 Pin Out Mapping To VME-P0 and VME64x-P2 |
VITA 36 D0.1 |
7/19/1998 abandoned |
W. Fischer |
PIM PMC I/O Module Standard. Greg Novak will renew this effort when VITA 32 is completed. |
VITA 37 PIRMA no draft
|
2/15/2000 |
J. Botte |
Product
Integrity Requirements for Mission Critical Applications. The sponsors
of this activity are: Nortel, MITRE, and CRANE. This task group will
quantify the commonalties between military and telecom requirements. A
Scope document for PIRMA was presented by M. MacPherson in September of
2000. |
ANSI VITA 38-2003 |
1/2003 |
M. Thompson |
System Management on VME- This 18 page ANSI VITA standard defines the implementation of an I2C IPMB bus on 5 J1/P1 VME pins. With the exception of the node board connector style this implementation is consistent with PICMG 2.9 System Management. |
ANSI VITA 39-2003 |
8/2003 released |
M. Franco |
PCI-X Auxiliary Standard for PMCs and Processor PMCs |
ANSI VITA 40-2003 |
2003 |
D. Cohen |
Service Indicators - Defines the colors, behaviors, placement, and labeling of service indicator lamps for boards, field replaceable units, and enclosures. |
ANSI VITA 41.0 -2006
|
5/2006 |
N. Steffensen |
VXS
VMEbus Switched Serial Standard Base Doc. The updates to the alignment
modules were implemented in the RTM document.. This 60 page document is
now a released ANSI VITA standard. |
ANSI VITA 41.1-2006
|
5/2006 |
M. German |
VXS
4X Infiniband (tm) Layer Protocol Standard is now a released ANSI -VITA
document and is 26 pages long. |
ANSI VITA 41.2-2006 |
5/206 |
E. Yu |
VXS 4X Serial Rapid IO Protocol Layer
Standard. This released ANSI/VITA document is 27 pages long. |
VITA 41.3-200X- revision 0.2 |
7/5/2005 |
M. German |
VXS 1000Mb/s Gigabit Ethernet Protocol Layer
Standard. This 26 page document reflects the changes that were
made as a result of the 12/20/04 ballot. |
VITA 41.4-200X draft 0.2 |
2/21/2005 |
M. Rush |
VXS
4x PCIxpress Protocol Layer Standard VXS.4 products will comply
with PCI Express Signal, Link, Transport, and Management layers in
order to maximize interoperability with other PCI Express hardware and
software products. This document is now at 24 pages. |
VITA 41.5-2006 draft
0.1
|
4/19/2006 |
D. Bosworth |
Aurora
Protocol over switched VXS backplane. The Aurrora protocol is designed
to be an ideal implementation for Xilinx Rocket IO. The initial draft
is 23 pages long. |
VITA 41.6-200X Draft 3
|
8/8/2008 |
K. Sheth |
VITA 41.6 VXS 1X Gigabit Ethernet Control Channel Standard. This standard will provide a 2-pair (4-wire) control channel mapped from the switch slot J1 to the J0 of each payload slot. Although this channel will make use of J0 payload connector pins that were previously reserved for future use (RFU) connector pairs in the switch slot that have previously been assigned to the IPMI bus will have to be reassigned. This new Gigabit Ethernet control channel will be used to initiate applications, configure processors, reprogram resources . This channel will be independent of any other fabric in a VXS system. This document passed the ANSI Sponsor ballot and is in the final ballot resolution phase. This document is now 35 pages long. |
VITA 41.7-200X draft 0.5a
|
1/25/2007 |
M. Munroe |
Processor
Mesh on VXS. This validation standard will define a new functional
backplane area consisting of a 4x redundant fully meshed backplane
segment compatible with the fabric switch slot channel assignments. By
extending the two central fabric channels, A and B, to each of these
slots and also assigning a minimum of two channels to rear IO, this
meshed segment will support application processes that require the
resources of more than two boards. Because this is a point-to-point
full mesh, this backplane segment will support FPGA SERDES IO protocols
such as Aurora or Altera Lite while leaving the central IO channel for
IO and management uses. By moving processor intensive functions
off the fabric switch cards less expensive fabric switches are now
practical. This document offers three different signal assignment
tables for VXS connector J1 which allow for "on-board" or
"off-board" system management controllers or the control plane GigE
switch.This draft
document has is currently 57 pages long. Draft 8 of a white paper which
has
implications for the processor slots was circulated to the reflector on
12/21/2006. and this document is awaiting review by the working group.
It may be necessary to reform the working group due to inactivity. |
VITA 41.8 no draft
|
9/2007 |
A. Reddig |
VITA 41.8 -
10Gigabit Ethernet on VXS. This document is in the planning stage with
no draft available. |
VITA 41.9 no draft
|
6/13/2003 |
J. Sherman |
VITA
41 and VITA 41.2 extended for 9U VME. This activity was abandoned. |
VITA 41.10-2003 rev 1.0 |
1/22/2003 |
S. Paavola |
Live
Insertion System Requirements for VXS Boards. This document has passed
working group ballot and is available as a trial use standard. |
VITA 41.11-2005 draft 0.6.8
passed VSO ballot ready to send to ANSI
|
7/15/2006 |
W. Dennen |
RTM
for VXS Switched Serial Standard. This document provides the mechanical
and electrical requirements for 6U x 80 mm rear transition modules for
VXS. A new board depth, new rear connectors and new alignment modules
are defined. The front panels mechanics and card orientation is the
same as defined by IEEE 1110.11. This document has now passed VITA
ballot and is ready to be sent to ANSI. This document is 23 pages long. |
ANSI-VITA 42.0-2008 |
12/2008 |
A. Reddig |
XMC
Switched Mezzanine Card Auxiliary StandardLayer Standard. This standard
will build on PMC
so that a socket on a carrier board will support both XMC and PMC
cards. The key mechanical dimensions remain the same. This is now a
released ANSI trial use standard and 42 pages long. |
ANSI-VITA 42.1 -2006
|
2/2006 |
R. Banton |
XMC
Switched Mezzanine Card: Parallel Rapid IO™ 8/16 LP-LVDS Protocol Layer
Standard |
ANSI-VITA 42.2 -2006 |
2/2006 |
P. Dozier |
XMC Serial Rapid IO Protocol Layer Standard.
This is a released ANSI/VITA standard which is 17 pages long. |
ANSI-VITA 42.3 -2006 |
2/2006 |
L. Brown |
XMC
PCIxpress IO Protocol Layer Standard This 36 page standard is a
released ANSI/VITA standard. |
VITA 42.4-200X draft 0.2 |
5/15/2005 |
K. Boyette |
XMC HyperTransport Protocol Layer Standard.
This document has not progressed in more than 4 years. |
VITA 42.5-200X no draft |
8/22/2005 |
A. Reddig |
Aurora Protocol over XMC mezzanine. This is
another proposed mapping of the Xilinx Rocket IO over the XMC mezzanine
standard. This is a proposed activity but no committee has yet been
formed. This document has not progressed in more than 4 years. |
VITA 42.6-200X draft 0.12 |
11/10/2009 |
Wai Ho Wu |
XMC 10 Gigabit Ethernet 4-Lane Protocol Layer
Standard. This document defines the implementation of 10G 4-lane XAUI
over the XMC socket. The document is now 19 pages long. |
VITA 42.10-200X draft 0.12 |
1/10/2006 |
L. Brown |
Pin
outs for XMC This “living” document is a registry of pin assignments
that have been defined by users. This is not a standard, but serves as
a forum to capture information regarding current practice. The
intention is to allow people to duplicate existing pin assignments
where practical. This document, however has not progressed in over 3
years. |
|
VITA 45S draft 0.91 |
7/21/2004 abandoned |
H.Strass |
Serial
VME This standard is intended to encapsulate the VME protocol within a
serial bit stream much as been done for SCSI, PCI and RapidIO.
Unfortunately there does not seem to be sufficient interest and this
may be tabled. This document has not progressed in over 5 years. |
ANSI-VITA 46.0-2007
|
10/2007 |
I.
Staznicky (J. Kwoc) |
VPX
Baseline Standard. This specification is intended to provide for
users: The advantage of high-speed interconnect technologies,
electrical compatibility with VMEbus and VMEbus software, framework for
heterogeneous architectures, 3U and 6U solutions and a mechanical
structure for harsh, rugged environments with the necessary cooling. V46 will support a
variety of multi-gigabit differential signaling including: serial Rapid
IO, PCI Express, PCIe Advanced Switching and full mesh fabrics. The
document now has an example of a 5-slot full mesh
that could
be used with PCI Express or Rapid IO. This document is now a released
ANSI-VITA standard and is 107 pages long |
ANSI-VITA 46.1-2007
|
10/2007 |
J. Kwok |
VMEbus
Signal Mapping on VPX. Parallel
VME64x signals on VITA 46. This 30 page document extends the VME64x bus
onto the VITA 46 backplane. The mapping takes up the J2 connector on
the backplane entirely. On the daughter card it requires use of a
single ended version of the MultiGig connector in position P2 but on
the backplane it is only a new set of signal assignments for the J2 but
the MultiGig does not have a separate version for single ended signals. |
VITA 46.2 no draft |
1/2005 |
t.b.d. |
Parallel
PCI on VITA 46 . I just changed this status to abandoned. This document
was proposed in January 2005 according to my records but there has not
been sufficient interest to move forward with. |
VITA 46.3-200X draft 0.9 |
2/24/2009 |
D. Toohey |
4x
Serial
Rapid IO on VITA 46 David Toohey has just begun updating this
document. A couple of pages may have been removed or condensed as
the document is now 21 pages (down from 24) and still has the Sept. 26,
2005 date on the front cover. An electrical loss budget was
proposed on 5/17/06. A decision is also being made to rename the
backplane connectors "J" and daughter card connectors "P". A glyph is
being considered and there is a question regarding the need for any
reserved P1 SE pins for future use. This document is now 24 pages
long.
The ballot for this document closed on March 13, 2009. |
VITA 46.4 draft 0.7 |
1/6/2009 |
Val Gueorguiev |
PCI
Express on VITA 46 . This document has preliminary pin outs and
is 20 pages long. There has been an extensive discussion of clock
distribution and use of REF clock. |
VITA 46.5-200X draft 0.1 |
6/24/2005 |
E. Kheyfets. |
Hypertransport
on VITA 46 This draft document is 29 pages long. |
VITA 46.6 no draft |
9/11/2007 |
|
Gigabit
Ethernet on VITA 46 Some work has recently taken place in VITA
46.0 to create a location for Gigabit Ethernet signals for both 3U and
6U form factors. On September 11 this document was discontinued and the
material will be covered in VITA 46.7 which will be 10G BASE KX-4 on J2 |
VITA 46.6 no draft |
3/9/2009 |
D. Toohey |
Gigabit
Ethernet Control Plane on VPX. This document will cover the
implementation of a Gigabit Ethernet Control Plane on VPX. This
document will be separate from the implementation of Gigabit and 10G
Ethernet serial fabrics used for data planes and expansiion planes on
VPX. Electrical requirements will be defined within VITA 68. This
effort does not yet have a first draft. |
VITA 46.7 draft 0.07 |
5/11/2009 |
S. Goedeke |
Ethernet
on VPX Fabric Connector. This document will define the implementation
of various Gigabit Ethernet protocols on the VPX fabric connector
J1/P1. This document will cover 10GBase-KX, 10G-BaseKX4, 1000Base-BX
and any other required Ethernet protocols being implemented as a serial
data plane on VPX. The document was intially being focused on VITA
46.20 but is now a general implementation focused on VITA 46 and VITA
65. This document will not address a Gigabit Control Plane which is the
subject of VITA 46.6. This document is currently 21 pages long. |
VITA 46.8 no draft |
2005 |
t.b.d. |
Infiniband
on VITA 46 |
VITA 46.9 draft 0.23 |
10/19/2009 |
J. Goldenberg |
XMC
and PMC Mezzanine IO Mapping on VITA 46. This document addresses
PMC/XMC mapping on VPX. Because of the potential for interoperability
issues and the competition for IO connector locations within VPX this
work was set aside for some time as the OpenVPX initiative began its
work. Now that that work is nearly complete, work on this document has
resumed. This document
is now 84 pages long. |
VITA 46.10 draft 0.10 |
9/17/2009 |
I. Straznicky |
Rear
Transition Module (RTM) for VITA 46. The backplane connector is
numbered from bottom to top on the rear side. Due to the connector
design and the requirement for a closed connector, row 1 is not
populated in the rear. For this reason there are only two
power
wafers but since the first two power wafers were redundant, all
voltages are available on the RTM. The VPX RTM is 81 mm long due to the
connector design. This document is now 39 pages
long. |
VITA 46.11 draft |
2005 |
t.b.d. |
ASI
(PCI Advanced Switching) on VITA 46 It appears with the addition of
Advanced Switching to VITA 46.4 that plans for this document may change
soon. |
VITA 46.11 no draft released
|
3/10/2009 |
D. Toohey |
System
Management for VPX. This will be an implementation of VITA 38 in a VPX
system. |
VITA 46.12 draft |
2005 |
S. Dewer |
Keying Standard for VITA 46 |
VITA 46.12 draft .3
|
11/7/2008 moved to VITA 66 |
B. Ford |
Fiberoptic
IO for VITA 46. This project has just been started. The work has begun
on this document. At the pressent time, Tyco and Amphenol have not
agreed on an interim optical connector design for specific
reasons. The following contact configurations are being
considered, MT style, MIL-T-29504
and expanded beam. Updated criteria for selection have been finalized
and recently Tyco made necessary statements regarding licensing.
Dimensions will be added to the document. The document is now 28 pages
long. This document was moved to VITA 66.0 and 66.1. |
VITA 46.14 draft .1
|
10/31/2009 moved to VITA 67 |
R. Normoyle |
Mixed
RF signals on VPX. The proposed connector is an eight position RF
module with float. Cable interface and EMI.RFI o-rings are available.
Tyco is preparing for environmental testing. Tyco made necessary
statements regarding licensing.
Dimensions will be added to the document. This document is now 27
pages long. This document was moved to VITA 67. |
VITA 46.20 draft .2
|
8/30/2008 |
N. Arshad |
Base
fabric switch. This document will define star and dual star Gigabit
fabrics in conjunction with the transport fabric. There is no document
at the present time however firm channel locations for 3U have been
proposed. Nauman is working actively on this document and hopes to
bring out a first draft in the next week. This document is 28 pages
long. The topologies covered by this document are now addressed within
VITA 65. |
VITA 46.21 draft .01
|
2/16/2009 |
S. Goedeke |
Base
fabric switch. This document will define star and dual star Gigabit
fabrics in conjunction with the transport fabric. There is no document
at the present time however firm channel locations for 3U have been
proposed. Nauman is working actively on this document and hopes to
bring out a first draft in the next week. The current document is 22
pages long. Since then we have resolved the choices to two 6U solutions
one 5-slot with up to 10 expansion slots. The other is 8 slots with up
to 16 expansions slots. The topologies covered by this document are now
addressed within VITA 65. |
VITA 46.x draft |
2005 |
t.b.d. |
Live Insertion on VITA 46 |
VITA 46.y draft |
2005 |
t.b.d. |
AMC on VITA 46 |
VITA 46.z draft |
1/17/2007 |
Martin Cassels |
Optical
Interface Connector on VITA 46. This is a proposed activity that is in
a collection stage. This activity is not formed into a formal
subcommittee yet. Watch for further details. This activity has been
restarted as of 8/25/2007. There will be a major presentation at the
November face-to-face. A "dot" standard is planned and there may
be two approaches, dense benign environment and sealed for a level 2
maintenance environment. |
ANSI VITA 47-R1 2005 (R2007)
|
1/2005 |
J. Robles |
Environments,
Design and Construction, Safety and Quality for Plug-In Units. This 21
page standard defines various environmental classes for modules of
three basic designs; forced-air, conduction and liquid flow-through
cooled modules. Within each of these broad divisions, there are
individual environmental definitions based on operating and
non-operating temperature, cooling cycle conditions, vibration levels
and operating shock. The document goes on to specify a test method and
specified values for each specified parameter. |
ANSI-VITA 47 -2005 (R2007)
|
0/2007 |
D. Golden |
Environments,
Design and Construction, Safety and Quality for Plug-In Units. The R1
version of this
document is now being revised to update cooling and to add a 3U
definition. This document is now an approved ANSI-VITA standard. This
version is 22 pages long. |
VITA 47r2 draft 0.14
|
1/6/2009 |
D. Golden |
Environments,
Design and Construction, Safety and Quality for Plug-In Units. The R2
version of this
document is now being prepared to address EMI and EMC per IEEE PAR 1688
and to add additional profiles required for VPX and rugged
MicroTCA. The revised document is now 23 pages long. |
VITA 48.0 draft 0.19a
|
5/17/2009 |
R. Banton (retired) |
Mechanical
Specifications for Microcomputers Using Ruggedized Enhanced Design
Implementation (REDI) Many proposed mechanical implementations shown.
This document introduces the features and concepts as well as card
size, basic slot pitch and known intellectual property that are
implemented as part of the air/conduction cooled 0.1 document and as
part of the liquid cooled implementation defined in the 0.2 document.
The introduction to this document previously cited nine patents on air
cooling but these references were removed and replaced with a statement
directing adopters to VITA for more information. The name
of the
standard was changed to change the acronym from ERDI to a
more pleasing sounding REDI. This draft no longer has the draft
number in the footer but now has the draft date in the footer. The
document is now 17 pages long. |
VITA 48.1 draft .21a
|
4/20/2009 |
M. Gust |
Mechanical
Specifications for Microcomputers Using REDI Air Cooling applied to
VITA 46. A great deal of
design work has gone into this document. This document is now 44
pages long. This document with a file name with the r0d21a has a cover
that says revision 14 dated 4/20/2009 and two different footers on
various pages, some including "Rev. D0.19" and some with "Rev. D0.20."
This document is nearly identical to draft 0.21 of the same date except
for some formatting changes. Inexplicably draft 21a has the previously
mentioned "draft 14 on the cover page and it's title no longer includes
the text "applied to VITA 46." |
VITA 48.2 draft 0.15 |
2/28/2009 |
M. Gust |
Mechanical
Specifications for Microcomputers Using REDI Air and Conduction Cooling
applied to VITA
46 . This is a 50 page document and provides for a sandwich
design with
heat management layers on both faces of the daughter card. |
VITA 48.3 draft 0.04 |
1/10/2007 |
R. Harvey |
Mechanical
Specifications for Microcomputers Using REDI Liquid Flow through
Cooling applied to VITA 46 . Parker Hannifin has proposed quick connect
ports that are approximately 0.45" diameter and provide significant
"gathering" as a replacement for a guide pin assembly. This extensive
document is now 41 pages in length. |
VITA 48.4
|
2008 |
R. Harvey |
Mechanical
Specifications for Microcomputers Using REDI Liquid Flow through
Cooling applied to VITA 46 with manifold above on 1.0" pitch. |
VITA 48.5 draft 6.0
|
8/28/2009 |
M. Guest |
Mechanical
Specifications for Microcomputers Using REDI Air flow through Cooling
as applied to VITA 46. The ballot for this document closed on
3/13/2009. It was at draft 3 and is 28 pages long. |
VITA 48.6
|
2008 |
R. Harvey |
Mechanical
Specifications for Microcomputers Using REDI Liquid Flow throug
Cooling applied to VITA 46 with manafold above and outboard on
0.8" pitch. |
ANSI-VITA 49.0-2009
|
5/2009 |
A. Kaiway |
|
ANSI-VITA 49.1-2009
|
5/2009 |
R. Normoyle |
|
VITA 50 draft 0.0 Cooling |
2/15/2006 |
R. Harvey |
Electronic
Cooling - Best Practices. This document which describes liquid cooling
of electronic
systems and is intended to provide an overview of methods, advantages,
disadvantages, relative effectiveness, relative reliability and
relative costs of various available methods. This new draft is 37 pages
long. |
VITA 51 CoP
|
1/17/2007 |
C. Falardeau |
A
"Committee of Preference" (CoE) has been formed with strong
participation. This group will work together to define best practices
for the implementation of Mil HDBK-217F Notice 2. At the moment, a
decision is pending on the location and operation of the web based Wiki. |
VITA 51.0 draft 6-26-07
Reliability
Prediction
|
6/26/2007 |
L. Bechtold |
Reliability
Prediction MIL HDBK-217. This document will be based on the methodology
used for another reliability standard, IEEE 1413.1. Guidelines 2005,
revised methods 20007 and new methods in 2008. This draft is now 40
pages long |
| VITA
51.1 draft 6-26-07 Reliability Prediction HDBK-217 daughter |
6/26/2007 |
P.
Miskelly |
Reliability Prediction. This document is intended to provide a common and consistent approach for their application to electronics modules. This working group represents a collaboration of members of various OEM suppliers and representatives from the DOD. The document is now 29 pages long. This document will serve as a an enhancement to Mil HDBK-217. |
VITA 51.2draft 6-26-07
Reliability
Prediction
|
3/2009 |
L. Bechtold |
Reliability
Prediction MIL HDBK-217. This document will be based on the methodology
used for another reliability standard, IEEE 1413.1. Guidelines 2005,
revised methods 20007 and new methods in 2008. This draft is now 40
pages long |
VITA 52.0 Lead Free,
Aerospace and High Performance Systems
|
11/2005 |
L. Bechtold |
Lead
Free Lori Bechtold of Boeing has presented the most recent update on
this activity. This work is to be based on GEIA-STD-005-1 draft 3.0
titled "Performance Standard for Aerospace and High Performance
Electronic Systems |
VITA 52.1 Mitigating
Effects of Tin Whiskers.
|
4/6/2005 |
L. Bechtold |
Lead Free Lori Bechtold of Boeing has presented the most recent update on this activity. This work is to be based on the 61 page document GEIA-STD-005-2 draft 3.2 titled "Standard for Mitigating the Effects of Tin Whiskers in Aerospace and High Performance Electronic Systems." For information regarding the GEIA see: http://www.geia.org |
VITA 52.2 Lead Free
Electronics Handbook
|
4/6/2005 |
L. Bechtold |
Lead Free Lori Bechtold of Boeing has presented the most recent update on this activity. This work is to be based on a 26 page document , GEIA-HB-0005-1 draft 3.1 titled "System Engineering Guidelines for Managing the Transition to Lead-Free Electronics. For information regarding the GEIA see: http://www.geia.org |
VITA TA 53- 200x draft 4
|
3/18/2009 |
S. Cecil |
COTS
Commercial Market Surveillance Activities. This standard is an attempt
to manage
commercial technology and track COTS
requests, product obsolescence, stock
status, and end of production for ten COTS working groups across the
country. This document just released its first draft which is now 22
pages long. At the 1/17/2007 VSO meeting S. Cecil reported that the
study group is ready to transition into Working Group Status as they
have just gained their third sponsor. ANSI balloting for this document
is planned for summer of 2009. An article in VME and Critical Systems
is planned. |
VITA 54.0 EPMA |
5/18/2005 |
K. Boyette |
ePMA Enhanced Platform Management Architecture. This standard defines an enhanced physical platform management architecture based on the AMD open license OPMA specification and the interface defined by IPMI. ePMA is intended to be suitable for use on commercial and ruggedized circuit card assemblies. This architecture will build upon VITA 38 and PICMG 2.9 which utilize the IPMI bus to implement a full platform management architecture. There has been no discernible activity in over a year. |
VITA 54.1 no draft yet |
5/18/2005 stagnant |
K. Boyette |
ePBMA Enhanced Management Structure for Backplane This standard defines a physical backplane interface standard for use on commercial and ruggedized circuit card assemblies. There has been no discernible activity in over a year. |
VITA 54.2 no draft yet |
5/18/2005 stagnant |
K. Boyette |
ePMMA Pluggable Management Module Architecture. This standard defines a pluggable management module suitable for use on commercial and ruggedized circuit card assemblies. There has been no discernible activity in over a year. |
VITA 55.0-2006 draft 0.6
|
11/10/2006 |
P. Burns |
|
VITA 55.1-2006 draft 0.1
|
11/10/2006 |
P. Burns |
|
|
12/11/2006 |
D. Slaton |
Express
Mezzanine Card Base Standard. This standard will define a hot pluggable
mezzanine card that will be compatible with VME and CompactPCI and use
a PMC like bezel. The card size will be 74 x 149 mm and it is expected
to use a edge card connector interface much like AMC. A X4 PCIxpress
interface will be a minimum requirement but other "fat pipe"
arrangements and common options are expected to have defined areas. At
the present time, the committee is meeting every other week. A new
connector decision is the most critical action to be completed. This
document is now 55 pages long. I cannot tell if this activity is
abandoned or mearly making glacial progress. |
VITA 56.1-200X draft 0.02 |
8/22/2006 glacial |
D. Slaton |
PCI on an Express Mezzanine Card Standard. Currently, this standard is considering how much grainularity of PCI Express to support. x1, x4, x8 and x16 will certainly be supported. The mention of x12 is just due to the actual number of signal pairs that are available for the link so this terminology is subject to change. The e-keying section needs to be completed. I cannot tell if this activity is abandoned or mearly making glacial progress. |
VITA 56.2-200X draft 0.01 |
11/30/2005 glacial |
D. Slaton |
Ethernet on an Express
Mezzanine Card Standard. This appears to be abandoned. |
VITA 56.4-200X5 draft 0.01 |
11/30/2005 glacial |
D. Slaton C. Eckert |
Serial Rapid IO on an Express
Mezzanine Card Standard. This appears to be abandoned. |
VITA 56.10-200X draft 0.01 |
11/30/2005 glacial |
D. Slaton C. Eckert |
Conduction Cooled Express Mezzanine Card
Standard. This appears to be abandoned. |
VITA 56.20-200X draft 0.02 |
12/11/2006 glacial |
D. Slaton C. Eckert |
General Purpose Interfaces on an Express Mezzanine Card Standard. Interfaces will include but not be limited to USB, SATA, RS232, RS422, RS485 etc. . . At the January '07 VSO meeting, the completion of the I/O specification was listed as the current goal. This document is now 9 pages long. I cannot tell if this activity is abandoned or mearly making glacial progress. |
ANSI-VITA 57.1 2008
|
7/2008 released |
M.
Devlin |
ANSI
VITA FPGA
Mezzanine Standard (FMC) define the form factor, signal
assignments for a
mezzanine card designed to support FPGAs. The single high module
is 69 mm x 139 mm. A 4 x
40 grid is defined from the SAMArray connector family.
Various stacking heights from 8.5 to 10 mm will be allowed. A card may
have both PMC and XMC sockets. This
document is 79 pages long. |
VITA 57.1 2009 draft 0.19
|
2/18/2009 |
M.
Devlin |
FPGA
Mezzanine Standard (FMC) draft will re-defined clocks signals
from the carrier card to the mezzanine card; CLK0_C2M_N, CLK0_C2M_P,
CLK1_C2M_N, CLK1_C2M_P. It is proposed that these signals will now be
redefined as additional ‘M2C’ signals. The work on this document is in
progress. |
VITA 57.2 200X draft .0
Driver IP
|
6/24/2006 |
M.
Devlin |
FPGA
Meta data description for physical support specified for IO. This first
draft is now 29 pages long. |
VITA 57.3 200X no draft
|
6/24/2006 |
M.
Devlin |
FPGA
driver IP Standard. This document will define the necessary Driver IP
that may
have
to be incorporated into an FPGA to interface to the above mezzanine
hardware standard. This first draft is now 29 pages long. |
| VITA 58.0
draft 0.8 |
8/27/2008 |
Dan Golden M. Humphrey D. Grisaffi Eron Strod |
Line
Replaceable Integrated Chassis (LRU) standard
defines the interface requirements necessary to implement a replaceable
chassis design. The document will include the design of truses or
stalks for power, electrical and optical connections as well as latches
for a Least Removable Unit (LRU) electrical package suitable for the
future land assault vehicle FLAS. The design concept is to be based
upon
previous work created by Carlson Engineering for the Department of
Defense. The initial draft document is 28 pages long. |
| VITA 58.1
draft 0.1 |
11-17-2009 |
Bruce Thomas |
Line
Replaceable Integrated Chassis (LRU) Liquid Cooled. This document will
define the interface requirements for a liquided cooled LRU. The
initial draft document is 22 pages long. |
VITA 59 200X draft 0.2
|
4/7/2008 |
Michael
Plannerer |
Rugged
System on Module Express (RSE). This standard will define the
implemention of Comm Express in a Eurocard form factor . This document
is now 46 pages long. |
VITA 60 200X no draft
|
9/2009 |
G.
Powers |
XMC Alternative Connector for OpenVPX. |
VITA 61-200X no draft
|
3/18/2009 |
B.
Grochmal |
Open
VPX
family of standards implemented on the Viper pin and socket connector
on 1.0" pitch. |
VITA 62
|
2009 |
Samtec
|
VITA
42 XMC implemented on a solder ball connector. This
activity was cancelled. |
VITA 62 draft 0.01
|
7/20/2009 |
Pat
Shaw |
A
Power Supply Standard for OpenVPX. This document is defining a COTS
power supply and the connector interface for use with OpenVPX. The
document is now 24 pages long. |
VITA 63 no draft
|
11/19/2009 |
J.
Demers |
A
Standard to define the implementation of OpenVPX
on the KVPX Hypertronix connector. |
VITA 64 no draft
|
11/19/2009 |
D.
Dix |
VPX
family of standards implemented on the Viper pin and socket
connector on 0.8" pitch. |
VITA 65 draft 1.03
|
12/12/2009 |
P.
Jha G. Rocco |
OpenVPX
System Standard. This document was developed initially by the technical
workng group of the OpenVPX Initiative. The initiative held its first
face-to-face meeting in March of 2009. As part of the memmorandum
of understanding for that trade association, the final document was
turned over to VITA and is now VITA 65. This standard will implement a
new descriptive language for module, slot backplane and system profiles
that can be used to define VPX system elements. It introduces the
terms, quad fat pipe, double fat pipe, fat pipe, thin pipe and
ultra-thin pipe for serial fabric channels used within VPX backplanes.
The standard will also define a standard module, slot and backplane
profiles that can be used for VPX development systems. The goal is to
simplify the implementation of VPX systems and to ensure
interoperability. The document is the focus of an intense writing
effort and is now 410 pages long. |
VITA 66.0 (46.12) draft
0.04
|
11/18/2009 |
B.
Ford |
Optical
Interconnect on VPX Base Standard. This document is the core of a
family of documents that will define the implementation of backplane
optical connectors on the VPX family of standards. The optical
connectors may occupy 6U connector locations J2/P2 through J6/P6 and
location J2/P2 on 3U VPX backplanes and cards. This document was
formerly VITA 46.12 and is now 15 pages long. |
VITA 66.1 (46.12) draft
0.51
|
12/3//2009 |
B.
Ford |
Optical
Interconnect on VPX - MT Variant. This document defines the
implementation of an MT optical backplane connector on cards and
backplanes built to the VPX family of Standards. This document
was
formerly VITA 46.12 and is now 19 pages long. |
VITA 67 (formerly 46.14)
no draft
|
10/31/2008 |
R.
Normoyle |
Analog RF Connector for OpenVPX. Ths document was formerly
VITA 46.14. This standard will cover the implementation of an 8 cavity
coaxial RF connector in position P6/J6 for 6U modules and a 4 or 8
cavity coaxial RF connector in connector position P2/J2 for 3U modules.
The existing 46.14 document is at draft 0.1 and is 27 pages long. |
VITA 68 draft 0.12
|
11/18/2009 |
B.
Sullivan |
This
is a channel requirements document that will cover the electrical
requirements for various signaling protocols being implemented within
the OpenVPX
family of standards. It is currently 17 pages long. |
VITA 69 draft 0.01
|
10/20/2009 |
B.
Ford |
A VITA Standard Glossary. This document will contain
glossary terms that have been developed in various VITA documents. The
document is currently 15 pages long. |
VITA 70 draft 0.20
|
10/20/2009 |
B.
Ford |
VITA
Standard Template. This is not a standard but simply the a standardized
template that can be used by VITA working groups to start a new
standard. |
|
|
|
||
VXI-1 Rev 3.0 VXIbus System |
|
11/24/2003 |
VMEbus Systems Specification covers the backplane, front panels, keying, modules, shielding and environmental specifications |
VXI-2 Rev 1.0 Extended Registers |
|
|
VXIbus Extended Register Based Devices and Extended Memory Device Specification |
VXI-6 Rev 1.0 VMEbus Mainframe Extender |
|
|
VXIbus Mainframe Extender Specification |
VXI-8 Rev 2.0 Cooling Characterization |
11/1997 |
|
VXIbus Cooling Characterization Methodology Specification |
VXI-11.3 draft 0.3 TCIP IEEE 488.2 Instrument Specification |
|
|
VXIbus interface specification for use with IEEE488.3 |
|
|
|
|
|
| LXI Consortium |
http://www.lxistandard.org |
||
| LXI
Standard Revision 1.0 |
9/23/2005 |
LXI
Consortium |
Lan Extension for
Instrumentation or LXI is a test equipment specification that used
Ethernet to connect various test equipment modules into a single
instrument. This document is 113 pages long and was driven by a
consortium founded by Agilent. |
| LxiSync Revision 1.0 |
9/23/2005 |
LXI
Consortium
|
This LxiSync
specification defines the API for controlling the arming, triggering,
and event functionality of LXI devices. This functionality applies to
LXI Class A and B devices but does not apply to the IVI instrument
class that may be supported by the device. The LxiSync Interface
Specification interprets an LXI instrument as one that can recognize
and respond to LXI trigger bus events or LAN based LXI events. This
document is 156 pages long. |
| LXI Standard
v1.0 s6.4.2 |
12/14/2005 |
LXI Consortium | Clarification for rule: 6.4.2 |
| LXI Standard
v1.0 s7.3.1 |
11/3/2005 |
LXI Consortium | Clarification for rule: 7.3.1 |
| LXI Standard v1.0 s7.3.1.1 | 11/17/2005 |
LXI Consortium | Clarification for rule: 7.3.1.1 |
| LXI Standard v1.0 s7.5 | 1/12/2006 |
LXI Consortium | Clarification for rule: s7.5 |
| LXI
Standard v1.0 s8.7.1 |
10/20/2005 |
LXI Consortium | Clarification for rule: 8.7.1 |
| LXI
Standard v1.0 s9.1 |
11/11/2005 |
LXI Consortium | Clarification for rule: 9.1 |
| LXI
Standard v1.0 s9.5 |
12/13/2005 |
LXI Consortium | Clarification for rule: 9.5 |
| LXI
Standard v1.0 s9.6 |
12/13/2005 |
LXI Consortium | Clarification for rule: 9.6 |
| LXI
Standard v1.0 s9.8 |
11/11/2005 |
LXI Consortium | Clarification for rule: 9.8 |
| Serial
Rapid IO Trade Assoc. |
http://www.rapidio.org |
||
| RapidIO
Spec. 1.3 Part 1 |
6/2005 |
IO
System Logical Layer. Defines many different types of
transactions. |
|
| RapidIO
Spec. 1.3 Part 2 |
6/2005 | Message
Passing Logical Layer |
|
| RapidIO
Spec. 1.3 Part 3 |
6/2005 | Common
Transport. |
|
| RapidIO
Spec. 1.3 Part 4 |
6/2005 | Parallel
Physical Layer Specification. |
|
| RapidIO
Spec. 1.3 Part 5 |
6/2005 | Global
Shared Logical Layer |
|
| RapidIO
Spec. 1.3 Part 6 |
6/2005 | Serial
Physical Layer Specification. |
|
| RapidIO
Spec. 1.3 Part 7 |
6/2005 | Interoperability
Physical Specification. This includes data headers, encoding, symbol
generation, buffer function, lane striping and the electrical
characteristics of the driver and receiver. |
|
| RapidIO
Spec. 1.3 Part 8 |
6/2005 | Error
Management Extensions. This document defines optional error management
including: registers, maintenance transactions, state capture, and
reporting. |
|
| RapidIO
Spec. 1.3 Part 9 |
6/2005 | Flow
Control Extensions. Optional extensions to manage traffic, congestion
and XON/XOFF controls |
|
| RapidIO
Spec. 1.3 Part 10 |
6/2005 | Data
Streaming Logical Layer - Phase 1. |
|
| RapidIO
Spec. 1.3 Part 11 |
6/2005 | Multi-cast
Extensions |
|
| RapidIO
Spec. 1.3 Annex 1 |
6/2005 | Software
and System "bring up" guide. Supplements the interoperability document. |
|
| RapidIO Spec. 1.2 | Earlier
specification still available. |
||
| Hardware Interop. Platform | 11/2002 |
Defines
mechanical and electrical requirements to endure interoperability.
(only available to members of T.A.) |
|
| Interop. Checklists Rev 1.3 | 9/2005 |
Device
Compliance Checklist: For compliance to revision 1.3 of the Serial
Rapid IO Specification (only available to members of the T.A.) |
|
| Bus Functional Model (BFM) | A
functional "C" model with a Verilog(tm) wrapper to be used to test for
interoperability. (available under license only to members of the T.A.). |
||
IEEE/ANSI Standards |
|
|
|
IEEE 181-1977 |
9/15/1993 |
O. Solomon |
IEEE Standard on Pulse Measurement and
Analysis by Objective Method. This standard was created by the IEEE
Instrument and Measurement Society for TC10 waveform analysis. |
IEEE 181-2003 |
7/11/2003 |
N. Paulter |
IEEE Standard on Transitions, Pulses, and
Related Waveforms. This standard combines IEEE standards 181-1977 and
194-1977 into one document |
IEEE 194-1977 |
9/15/1993 |
O. Solomon |
IEEE Standard Pulse Terms and Definitions.
This 63 page document defined the nomenclature used for the pulse
measurement
technique. This material was incorporated into IEEE 181-2003. |
IEEE 696-1983 Interface Devices |
6/10/1982 |
M. Garetz |
S-100bus This standard applies to interface
systems for computer system components interconnected by way of a
100-line parallel backplane commonly known as the S-100 bus. |
IEEE P 802.1ag |
7/10/2006 |
A.A.Jeffree |
P802.1ag Standard for Local and Metropolitan Area Networks Virtual Bridged Local Area Networks Amendment 5: Connectivity Fault Management |
IEEE 802.3-2002 |
5/13/2002 |
|
Includes
10/100/1000 BASE-T signaling over structured wiring. 802.3-1998
superceeded 802.3-1995 and the new features adopted as versions ab, ac
and ad were incorporated into 802.3-2002 which in turn superceeded
802.3-1998. |
IEEE 802.3ae |
12/22/2002 |
|
Includes
10/100/1000 BASE-T signaling over structured wiring. The contents of
this document were incorporated into 802.3-2003. |
IEEE 802.3af |
9/22/2003 |
|
DTE
power via MDI also known as Power over Ethernet. The content of
this document was uncorporated into 802.3-2003. |
IEEE 802.3ap |
2/14/2007 |
A. Healey |
10
Gigabit Ethernet Backplane standard. This Ethernet document defines
three new Ethernet standards for backplane implementations. These
versions are intended to function across two backplane to daughter card
connector interfaces and 30 inches of unimproved FR-4. The single
channel implementation offers 10 Gigabites per second bi-directional
Ethernet. The three implementations are 1000BASE-KX, 10GBASE-KX4 and
10GBASE-KR. Because this is a generic backplane implementation, no
specific connectors are defined. Furthermore many of the basic
electrical performance characteristics are addressed with informative
language rather than specific normative requirements. This group worked
for two years and no greater level of agreement was possible. Draft D33
was the version of the document that was balloted and was 199 pages
long. |
IEEE 802.3 100 Gigabit
Ethernet BP Study Group
|
study group |
J. Joergen |
Just
as IEEE 802.3ap was ratified, a new study group was formed to begin
work on a 100 Gigabit Backplane Ethernet Study Group. It is
believed that the goal of this standard will be 100 Gigabit Ethernet
over four lanes of 25 Gigabit per second capability. |
IEEE 802.3-2003 |
12/9/2003 |
|
Systems
Networking
Guide: How to Optimize Your Network Using the ISO/IEC 8802-3 Carrier
Sense Multiple Access with Collision Detection (CSMA/CD) Standard. This
has been updated on a regular basis. The version ending in -2003
incorporates versions ae, af and ag and all the features that were
previously incorporated into 802.3-2002. |
IEEE 802.3 EFM |
3/30/2006 |
|
Ethernet in
the First Mile (EFM) standard. This is a comprehensive document that
covers the entire family of Ethernet standards. It introduces the
terminology and evolution of the various standards and helps lay out
the essential considerations that a business model must consider when
chosing a specific Ethernet technology. This document was, during
development, P802.3ah |
IEEE P 802.3amREV |
5/11/2005 |
D. J. Law |
Information technology -- Telecommunications and information exchange between systems -- Local and metropolitan area networks -- specific requirements Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications. This draft was accepted and became IEEE802.3-2005 in December of 2005 and was published in 2006. |
IEEE 802.3-2005 |
2/21/2006 |
|
Systems
Networking
Guide: How to Optimize Your Network Using the ISO/IEC 8802-3 Carrier
Sense Multiple Access with Collision Detection (CSMA/CD) Standard. This
has been updated on a regular basis. The version ending in -2005 was
known during development as 802.3-REVam and incorporated the features
of 802.3-2003, ah and av |
IEEE P 802.3 2005-Cor 1D2.0
|
9/28/2006 |
D. J. Law |
P802.3-2005-Cor_1
Information technology Telecommunications and information exchange
between systems Local and metropolitan area networksSpecific
requirements Part 3: Carrier Sense Multiple Access with Collision
Detection (CSMA/CD) access method and physical layer specifications
Corrigendum 1. This updates 802.3-2005 with the changes needed to fully
implement the af revision. |
IEEE P. 802.3an D4.0
|
10/24/2006 |
R. Grow |
This update to Gigabit Ethernet has now
completed sponsor ballot, it is approved and submitted to REVCOM |
IEEE P 802.3ap D3.3 |
1/27/2007 |
A. Healey |
CSMA/CD Access Method and Physical Layer Specifications Amendment: Ethernet Operation over Electrical Backplanes 10 Gig single channel (if they do this over a single channel, and specify the path adequately, it will be a very significant accomplishment) http://www.ieee802.org/3/ap/ On February 13, 2007 draft 3.3 completed its third recirculation ballot successfully with no negative comments. This 199 page draft will be presented at the next IEEE REV Com meeting and will then be prepared for publication and public release. |
IEEE P 802.3aq D4.0
|
7/20/2006 |
D. J. Law |
P802.3aq Information technology -- Telecommunications and information exchange between systems -- Local and metropolitan area networks -- specific requirements Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications Amendment: Physical Layer and Management Parameters for 10 Gb/s Operation, Type 10GBASE-LRM |
IEEE P 802.3as D3.3
|
8/18/2006 |
D. J. Law |
P802.3as Information technology - Telecommunications and information exchange between systems - Local and metropolitan area networks - Specific requirements Part 3: Carrier sense multiple access with collision detection (CSMA/CD) Amendment: Frame format extensions |
IEEE 802.11b |
|
|
Wireless LAN |
IEEE 802.11g |
|
|
Wireless LAN |
IEEE Std 896.1-1991 |
9/26/1991 withdrawn |
P. Borrill |
IEEE
Standard for Futurebus+ - Logical
Protocol Specification. This standard was withdrawn December 9, 1997 |
IEEE Std 896.2-1991 |
9/26/1991 withdrawn |
J. George |
IEEE
Standard
for Futurebus+ - Physical Layer and Profile Specification. This
standard was withdrawn December 9, 1997 |
IEEE P896.3a |
10/1994 |
M. Munroe |
Recommended Electrical Practices for Futurebus. This standard was to define the backplane electrical requirements for incident wave switching on Futurebus backplanes. The extraordinarily high di/dt of a 256bit wide parallel, multi-drop bus environment was defined which established requirements for termination response. I am not sure why Bill Schneider's name is associated with the PAR. M. Munroe opened the PAR and David Wright was the significant additional contributor. This PAR was withdrawn by the IEEE. |
IEEE Std 996-1990 |
1991 |
S. Hopkinson |
PC-AT Standard for a Personal Computer Bus |
IEEE Std 1014-1987 |
3/28/1988 |
Sven Rau
Max Loesel Craig McKenna Cecil Kaplinsky J. Black Shlomo Pri-Tal Lyman Hevle W. Fischer M. Pauker E. Waltz |
IIEEE Standard for A Versatile Backplane Bus: VMEbus – IEEE 1014/D1.2 (also IEC 821Bus) which was based upon the VMEbus Specification Manual Revision C.1 first published by VITA. Lyman Hevle is credited with naming the new architecture VME. The VMEbus was based upon Motorola’s VERSAbus which was discussed in a 1981 publication. John Black lead the development of VERSAmodule and Sven Rau and Max Loesel first prototyped the Versabus adaptation in the Eurocard Format which appeared in October 1981 as VERSAmodule E. John Black and Craig McKenna and Cecil Kaplinsky authored the first draft of the VMEbus specification which as Revision A was placed into the public domain also in 1981. Revision B followed in 1982 and the European standard SC47B was begun with Mira Pauker. Revision C and C.1 were authored by John Black and Shlomo Pri-Tal following a meeting in 1983 that included Craig McKenna, Mira Pauker and W. Fischer. IEEE 1014/D1.2 was begun in 1983 with John Black as chair. IEC 821 was the equivalent project. The VME International Trade Association (VITA) was founded by Lyman Hevel in 1985 following the October 1985 publication of VMEbus Specification Manual Revision C.1 Other contributors to the VMEbus were Eike Waltz and Paul Borril. IEEE 1014 is not identified as "stabilized" by the IEEE but I am not sure why not as it has not been reissued which is supposed to happen for all active IEEE documents every five years. |
IEEE P-1014 |
6/26/1995 withdrawn |
K. Clohessy |
IEEE Standard
for 32/64-bit Versatile Backplane Bus VMEbus. This PAR was withdrawn
and is no longer endorsed by the IEEE. Kim Clohessy died in May 2006
after a battle with cancer. He is missed greatly by all who knew and
worked with him on many IEEE and VITA standards. This work was
completed within VITA's VSO and is ANSI VITA 1.0 American National
Standard for VME64. |
IEEE Std 1014.1-1994 |
6/26/1995 withdrawn |
W. Fischer |
IEEE
Standard for a Futurebus+ VME 64 Bridge. This standard was withdrawn by
the IEEE on May 1, 2000. |
IEEE Std 1096-1988 |
5/19/1989 withdrawn |
S. PriTal |
IEEE Standard
for Multiplexed High-Performance Bus Structure VSB. This defined the
Address lines AD00-AD31 on rows A and C. One of the first P2 VME buses.
This standard was withdrawn by the IEEE on December 9, 1997. |
IEEE Std 1101-1987 |
withdrawn |
E. Waltz |
IEEE Standard for Mechanical Core Specifications for Microprocessors. Withdrawn Standard. Withdrawn 12/21993. No longer endorsed by the IEEE. |
IEEE Std 1101.1-1998 |
9/28/1998 |
E. Waltz |
Standard for Mechanical Core Specification for Microcomputers Using IEC 603-2 Connectors |
IEEE Std 1101.2-1992 |
6/18/1992 |
Kim Clohessy |
Standard for Conduction Cooled Eurocards. Mechanical characteristics of conduction-cooled versions of Eurocard subracks. The aim is to ensure mechanical compatibility of conduction-cooled rugged card assemblies with commercial 6U Eurocard subracks. |
IEEE Std 1101.3-1992 |
withdrawn |
K. Clohessy |
IEEE Mechanical Standard for Conduction-Cooled and Air-Cooled 10 SU Modules. Withdrawn Standard. Withdrawn Date: Jan 15, 2001. No longer endorsed by the IEEE. |
IEEE Std 1101.4-1993 |
withdrawn |
J.Toy |
IEEE Standard for Military Module, Format E Form Factor. The mechanical design requirements for a military module, format E form factor are established. Withdrawn Standard. Withdrawn Date: Jan 15, 2001. No longer endorsed by the IEEE. |